Average and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm, and 45nm CMOS Technology for a High Speed SRAMs
نویسندگان
چکیده
A lot of consideration has been given to problems arising due to power dissipation. Different ideas have been proposed by many researchers from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between the power, delay and area. This is why; the designers are required to choose appropriate techniques that satisfy application and product needs. Another important component of power which contributes to power dissipation is Dynamic Power. This power is increasing due to prolonged use of the electronic equipments. This is due to the fact that now-a-days people are working on electronic systems from morning till night; it may be a mobile phone or a laptop or any other equipment. This paper deals with the estimation of two components of power i.e. static power (when device is in the standby mode) and the average power (average amount of energy consumed with respect to time) of a 6T and 7T SRAM (Static Random Access Memory) bit-cell at 180nm, 90nm, and 45nm CMOS Technology. This is done in order to estimate the power required for a high speed operation of 6T and 7T SRAM bit-cell.
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